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freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc33887 rev. 14.0, 3/2011 freescale semiconductor technical data ? freescale semiconductor, inc., 2007 - 2011. all rights reserved. 5.0 a h-bridge with load current feedback the 33887 is a monolithic h-bridge power ic with a load current feedback feature making it ideal for closed-loop dc motor control. the ic incorporates internal cont rol logic, charge pump, gate drive, and low r ds(on) mosfet output circuitry. the 33887 is able to control inductive loads with continuous dc load currents up to 5.0 a, and with peak current active limiting between 5.2 a and 7.8 a. output loads can be pulse width modulated (pwm-ed) at frequencies up to 10 khz. the load current feedback f eature provides a proportional (1/ 375th of the load current) constant-current output suitable for monitoring by a microcontroller?s a/ d input. this feature facilitates the design of closed-loop torque/s peed control as well as open load detection. a fault status output pin report s undervoltage, short circuit, and overtemperature conditions. two independent inputs provide polarity control of two half-bridge totem-po le outputs. two disable inputs force the h-bridge outputs to tr i-state (exhibit high-impedance). the 33887 is parametrically specif ied over a temperature range of -40 c t a 125 c and a voltage range of 5.0 v v+ 28 v. operation with voltages up to 40 v with derating of the specifications. features ? fully specified operation 5.0 v to 28 v ? limited operation with reduced performance up to 40 v ?120 m r ds(on) typical h-bridge mosfets ? ttl/cmos compatible inputs ? pwm frequencies up to 10 khz ? active current limiting (regulation) ? fault status reporting ? sleep mode with current draw 50 a (inputs floating or set to match default logic states) figure 1. 33887 simplified application diagram ordering information device temperature range (t a ) package mc33887apvw/r2 -40 c to 125 c 20 hsop mc33887pfk/r2 36 pqfn mc33887pek/r2 54 soicw-ep vw suffix (pb-free) 98ash70702a 20-pin hsop bottom view ek suffix (pb-free) 98asa10506d 54-pin soicw-ep fk suffix 98asa10583d 36-pin pqfn 33887 h-bridge 33887 ccp in1 in2 d1 en fs mcu pgnd d2 motor out1 out2 agnd v+ fb 6.0 v v+ fb in out out out out out a/d
analog integrated circuit device data 2 freescale semiconductor 33887 internal block diagram internal block diagram figure 2. 33887 simplifi ed internal block diagram out1 out2 pgnd agnd ccp vpwr en in1 in2 d1 d2 fs fb charge pump current limit, overcurrent sense & feedback circuit undervoltage over control logic temperature gate drive 5.0 v regulator 25 a 8 a ( each )
analog integrated circuit device data freescale semiconductor 3 33887 pin connections pin connections figure 3. 33887 pin connections table 1. 33887 hsop pin definitions a functional description of each pin can be found in the functional pin descriptions section, page 21 . pin pin name formal name definition 1 agnd analog ground low-current analog signal ground. 2 fs fault status for h-bridge open drain active low fault status output requiring a pull-up resistor to 5.0 v. 3 in1 logic input control 1 logic input control of out1 (i.e., in1 logic high = out1 high). 4 , 5, 16 v+ positive power supply positive supply connections 6 , 7 out1 h-bridge output 1 output 1 of h-bridge. 8 fb feedback for h-bridge current sensing feedback output providing ground referenced 1/375th (0.00266) of h-bridge high-side current. 9 ? 12 pgnd power ground high-current power ground. 13 d2 disable 2 active low input used to simultaneous ly tri-state disable both h-bridge outputs. when d2 is logic low, both outputs are tri-stated. 14 , 15 out2 h-bridge output 2 output 2 of h-bridge. 17 ccp charge pump capacitor external reservoir capacitor connecti on for internal charge pump capacitor. 18 d1 disable 1 active high input used to simultaneous ly tri-state disable both h-bridge outputs. when d1 is logic high, both outputs are tri-stated. 19 in2 logic input control 2 logic input control of out2 (i.e., in2 logic high = out2 high). 20 en enable logic input enable control of device (i.e., en logic high = full operation, en logic low = sleep mode). tab/pad thermal interface exposed pad thermal interface exposed pad thermal interface for sinking heat from the device. note must be dc-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into ic substrate. en agnd in2 d1 ccp v+ out2 out2 d2 pgnd pgnd fs v+ out1 out1 fb pgnd pgnd in1 v+ 1 2 3 4 5 6 7 8 9 10 20 19 16 15 14 13 12 11 18 17 tab tab
analog integrated circuit device data 4 freescale semiconductor 33887 pin connections figure 4. 33887 pin connections table 2. pqfn pin definitions a functional description of each pin can be found in the functional pin descriptions section, page 21 . pin pin name formal name definition 1, 7, 10, 16, 19, 28, 31 nc no connect no internal connection to this pin. 2 d1 disable 1 active high input used to simultaneous ly tri-state disable both h-bridge outputs. when d1 is logic high, both outputs are tri-stated. 3 in2 logic input control 2 logic input control of out2 (i.e., in2 logic high = out2 high). 4 en enable logic input enable control of device (i.e ., en logic high = full operation, en logic low = sleep mode). 5, 6, 12, 13, 34, 35 v+ positive power supply positive supply connections. 8 agnd analog ground low-current analog signal ground. 9 fs fault status for h-bridge open drain active low fault status output requiring a pull-up resistor to 5.0 v. 11 in1 logic input control 1 logic input control of out1 (i.e., in1 logic high = out1 high). 14, 15, 17, 18 out1 h-bridge output 1 output 1 of h-bridge. 20 fb feedback for h-bridge current feedback output providing ground referenced 1/375th ratio of h-bridge high-side current. 21? 26 pgnd power ground high-current power ground. 27 d2 disable 2 active low input used to simultaneous ly tri-state disable both h-bridge outputs. when d2 is logic low, both outputs are tri-stated. 29, 30, 32, 33 out2 h-bridge output 2 output 2 of h-bridge. 36 ccp charge pump capacitor external reservoir capacitor connec tion for internal charge pump capacitor. pad thermal interface exposed pad thermal interface exposed pad thermal interface for sinking heat from the device. note: must be dc-coupled to analog ground and power ground via very low impedance path to prevent injecti on of spurious signals into ic substrate. d2 nc 28 27 26 25 24 23 22 21 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 pgnd pgnd pgnd pgnd pgnd pgnd in2 d1 en v+ v+ nc agnd fs v+ ccp v+ out2 out2 nc out2 out2 v+ in1 v+ out1 out1 nc out1 out1 20 fb 19 nc 10 nc 1 nc transparent top view of package
analog integrated circuit device data freescale semiconductor 5 33887 pin connections figure 5. 33887 pin connections table 3. soicw-ep pi n definitions a functional description of each pin can be found in the functional pin descriptions section, page 21 . pin pin name formal name definition 1? 4, 51? 54 pgnd power ground high-current power ground. 5 ? 7, 9, 14, 19 ? 22, 27 ? 29, 33 ? 36, 41, 46, 48 ? 50 nc no connect no internal connection to this pin. 8 d2 disable 2 active low input used to simultaneous ly tri-state disable both h-bridge outputs. when d2 is logic low, both outputs are tri-stated. 10 ? 13 out2 h-bridge output 2 output 2 of h-bridge. 15 ? 18, 37 ? 40 v+ positive power supply positive supply connections. 23 ccp charge pump capacitor external reservoir capacitor connec tion for internal charge pump capacitor. 24 d1 disable 1 active high input used to simultaneous ly tri-state disable both h-bridge outputs. when d1 is logic high, both outputs are tri-stated. 25 in2 logic input control 2 logic input control of out2 (i.e., in2 logic high = out2 high). 26 en enable logic input enable control of device (i.e ., en logic high = full operation, en logic low = sleep mode). 30 agnd analog ground low-current analog signal ground. 31 fs fault status for h-bridge open drain active low fault status output requiring a pull-up resistor to 5.0 v. 32 in1 logic input control 1 logic input control of out1 (i.e., in1 logic high = out1 high). pgnd nc v+ v+ v+ v+ nc nc nc nc ccp d1 in2 en nc nc nc out2 out2 out2 out2 nc nc d2 pgnd pgnd pgnd pgnd nc v+ v+ v+ v+ nc nc nc nc in1 fs agnd nc nc nc nc out1 out1 out1 out1 nc nc fb pgnd pgnd pgnd 54 40 .35 34 33 32 31 30 29 28 39 38 37 36 47 46 45 44 43 42 41 51 50 49 48 53 52 1 15 20 21 22 23 24 25 26 27 16 17 18 19 8 9 10 11 12 13 14 4 5 6 7 2 3 transparent top view of package
analog integrated circuit device data 6 freescale semiconductor 33887 pin connections 42 ? 45 out1 h-bridge output 1 output 1 of h-bridge. 47 fb feedback for h-bridge current feedback output providing ground referenced 1/375th ratio of h-bridge high-side current. pad thermal interface exposed pad thermal interface exposed pad thermal interface for sinking heat from the device. note must be dc-coupled to analog ground and power ground via very low impedance path to prevent injecti on of spurious signals into ic substrate. table 3. soicw- ep pin definitions a functional description of each pin can be found in the functional pin descriptions section, page 21 . pin pin name formal name definition
analog integrated circuit device data freescale semiconductor 7 33887 electrical characteristics maximum ratings electrical characteristics maximum ratings maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit electrical ratings supply voltage (1) v+ -0.3 to 40 v input voltage (2) v in - 0.3 to 7.0 v fs status output (3) v fs -0.3 to 7.0 v continuous current (4) i out 5.0 a dh suffix hsop esd voltage (5) human body model each pin to agnd each pin to pgnd each pin to v+ each i/o to all other i/os machine model v esd1 v esd1 v esd1 v esd1 v esd2 1000 1500 2000 2000 200 v vw suffix hsop, soicw-ep, and pqfn esd voltage (5) human body model machine model v esd1 v esd2 2000 200 v thermal ratings storage temperature t stg - 65 to 150 c operating temperature (6) ambient junction t a t j - 40 to 125 - 40 to 150 c peak package reflow temperature during reflow (7) , (8) t pprt note 8. c notes 1 performance at voltages greater than 28v is degraded.see electrical performance curves on page 18 and 19 for typical performance. extended operation at higher voltages has not been fully c haracterized and may reduce the operational lifetime. 2 exceeding the input voltage on in1, in2, en, d1, or d2 may cause a malfunction or permanent damage to the device. 3 exceeding the pull-up resistor voltage on the open drain fs pin may cause permanent damage to the device. 4 continuous current capability so long as junction temperature is 150 c. 5 esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ). 6 the limiting factor is junction temperatur e, taking into account the power dissipatio n, thermal resistance, and heat sinking p rovided. brief nonrepetitive excursions of junction temperature above 150 c can be tolerated as long as durat ion does not exceed 30 seconds maximum. (nonrepetitive events are defined as not occurring more than once in 24 hours.) 7 pin soldering temperature limit is for 10 seconds maximum durat ion. not designed for immersion so ldering. exceeding these limi ts may cause malfunction or permanent damage to the device. 8. freescale?s package reflow capability meets pb-free requir ements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pr efixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data 8 freescale semiconductor 33887 electrical characteristics maximum ratings thermal resistance (and package dissipation) ratings (9) , (10) , (11) , (12) junction-to-board (bottom exposed pad soldered to board) hsop (6.0 w) pqfn (4.0 w) soicw-ep (2.0 w) r jb ~7.0 ~8.0 ~9.0 c/w junction-to-ambient, natural conv ection, single-layer board (1s) (13) hsop (6.0 w) pqfn (4.0 w) soicw-ep (2.0 w) r ja ~ 41 ~ 50 ~ 62 c/w junction-to-ambient, natural convec tion, four-layer board (2s2p) (14) hsop (6.0 w) pqfn (4.0 w) soicw-ep (2.0 w) r jma ~ 18 ~ 21 ~ 23 c/w junction-to-case (exposed pad) (15) hsop (6.0 w) pqfn (4.0 w) soicw-ep (2.0 w) r jc ~ 0.8 ~1.2 ~2.0 c/w notes 9 the limiting factor is junction temperatur e, taking into account the power dissi pation, thermal resistance, and heat sinking. 10 exposed heatsink pad plus the power and ground pins comp rise the main heat conduction paths. the actual r jb (junction-to-pc board) values will vary depending on solder thic kness and composition and copper trace thi ckness. maximum current at maximum die temperature represents ~ 16 w of conduction loss heating in the diagonal pai r of output mosfets. therefore, the r jc -total must be less than 5.0 c/w for maximum load at 70c ambient. modul e thermal design must be planned accordingly. 11 thermal resistance between the die and the printed circuit boar d per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 12 junction temperature is a function of on-chip power dissipation, package thermal re sistance, mounting site (board) temperatur e, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 13 per semi g38-87 and jedec jesd51-2 with the single-layer board (jesd51-3) horizontal. 14 per jedec jesd51-6 with the board horizontal. 15 indicates the maximum thermal resistance between the die and the ex posed pad surface as measured by the cold plate method (mi l spec-883 method 1012.1) with the cold plate temperature used for the case temperature. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. rating symbol value unit
analog integrated circuit device data freescale semiconductor 9 33887 electrical characteristics static electrical characteristics static electrical characteristics table 4. static elec trical characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power supply operating voltage range (16) v+ 5.0 ? 28 v sleep state supply current (17) i out = 0 a, v en = 0 v i q (sleep) ? 25 50 a standby supply current i out = 0 a, v en = 5.0 v i q (standby) ? ? 20 ma threshold supply voltage switch-off switch-on hysteresis v+ (thres-off) v+ (thres-on) v+ (hys) 4.15 4.5 150 4.4 4.75 ? 4.65 5.0 ? v v mv charge pump charge pump voltage v+ = 5.0 v 8.0 v v+ 28 v v cp - v+ 3.35 ? ? ? ? 20 v control inputs input voltage (in1, in2, d1, d2 ) threshold high threshold low hysteresis v ih v il v hys 3.5 ? 0.7 ? ? 1.0 ? 1.4 ? v input current (in1, in2, d1) v in - 0.0 v i inp - 200 - 80 ? a input current ( d2 , en) v d2 = 5.0 v i inp ? 25 100 a notes 16 specifications are characte rized over the range of 5.0 v v+ 28 v. see see electrical performance curves on page 18 and 19 and the see functional description on page 21 for information about operation outside of this range. 17 i q (sleep) is with sleep mode function enabled.
analog integrated circuit device data 10 freescale semiconductor 33887 electrical characteristics static electrical characteristics power outputs (out1, out2) output on-resistance (18) 5.0 v v+ 28 v, t j = 25c 8.0 v v+ 28 v, t j = 150c 5.0 v v+ 8.0 v, t j = 150c r ds(on) ? ? ? 120 ? ? ? 225 300 m active current limiting threshold (via internal constant off-time pwm) on low-side mosfets (19) i lim 5.2 6.5 7.8 a high-side short circuit detection threshold i sch 11 ? ? a low-side short circuit detection threshold i scl 8.0 ? ? a leakage current (20) v out = v+ v out = ground i out(leak) ? ? 100 30 200 60 a output mosfet body diode forward voltage drop i out = 3.0 a v f ? ? 2.0 v overtemperature shutdown thermal limit hysteresis t lim t hys 175 10 ? ? 225 30 c high-side current sense feedback feedback current i out = 0 ma i out = 500 ma i out = 1.5 a i out = 3.0 a i out = 6.0 a i fb ? 1.07 3.6 7.2 14.4 ? 1.33 4.0 8.0 16 600 1.68 4.62 9.24 18.48 a ma ma ma ma fault status (21) fault status leakage current (22) v fs = 5.0 v i fs (leak) ? ? 10 a fault status set voltage (23) i fs = 30 0 a v fs (low) ? ? 1.0 v notes 18 output-on resistance as measured from output to v+ and ground. 19 active current limitation applies only for the low-side mosfets. 20 outputs switched off with d1 or d2 . 21 fault status output is an open drain output requiring a pull-up resistor to 5.0 v. 22 fault status leakage current is measured with fault status high and not set. 23 fault status set voltage is measured with fault status low and set with i fs = 300 a. table 4. static el ectrical characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power supply
analog integrated circuit device data freescale semiconductor 11 33887 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electrical characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit timing characteristics pwm frequency (24) f pwm ? 10 ? khz maximum switching frequency during active current limiting (25) f max ? ? 20 khz output on delay (26) v+ = 14 v t d (on) ? ? 18 s output off delay (26) v+ = 14 v t d (off) ? ? 18 s i lim output constant-off time for low-side mosfets (27) , (28) t a 15 20.5 26 s i lim blanking time for low-side mosfets (29) , (28) t b 12 16.5 21 s output rise and fall time (30) v+ = 14 v, i out = 3.0 a t f , t r 2.0 5.0 8.0 s disable delay time (31) t d (disable) ? ? 8.0 s power-on delay time (32) t pod ? 1.0 5.0 ms wake-up delay time (32) t wud ? 1.0 5.0 ms output mosfet body diode reverse recovery time (33) t r r 100 ? ? ns notes 24 the outputs can be pwm-controlled from an external source. th is is typically done by hold ing one input high while applying a pwm pulse train to the other input. the maxi mum pwm frequency obtainable is a compromise between switching losses and switching frequency. see typical switching waveforms, figures 12 through 19 , pp. 14? 17 . 25 the maximum switching frequency during active current limiting is internally implemen ted. the internal cu rrent limit circuitr y produces a constant-off-time pulse-width modulation of the output curr ent. the output load?s inductance, capacitance, and resistance characteristics affect the total switching period (off-tim e + on-time) and thus the pw m frequency during current limit. 26 output delay is the time duration from the midpoint of the in1 or in2 input signal to the 10% or 90% point (dependent on the transition direction) of the out1 or out2 signal. if the output is transiti oning high-to-low, the delay is from the midpoint of the input signal to the 90% point of the output response signal. if the output is transi tioning low-to-high, the delay is from the midpoint of the input signal to the 10% point of the output response signal. see figure 6 , page 12 . 27 i lim output constant-off time is the time during which the internal constant-off time pwm current regulation circuit has tri-stated the output bridge. 28 load currents ramping up to the current regul ation threshold become limited at the i lim value. the short circuit currents possess a di/dt that ramps up to the i sch or i scl threshold during the i lim blanking time, registering as a short circuit event detection and causing the shutdown circuitry to force the output in to an immediate tri-state latch-off. see figures 10 and 11 , page 13 . operation in current limit mode may cause junction temperatures to rise. junction temperatures above ~160 c will cause the output current limit threshold to progressively ?fold back?, or decre ase with temperature, until ~175 c is reached, after which the t lim thermal latch-off will occur. permissible operation within this fold-bac k region is limited to nonrepetitive transie nt events of duration not to exceed 30 se conds. see figure 9 , page 12 . 29 i lim blanking time is the time during which the current regulation th reshold is ignored so that th e short-circuit detection thresho ld comparators my have time to act. 30 rise time is from the 10% to the 90% level and fall time is from the 90% to the 10% level of the output signal. see figure 8 , page 12 . 31 disable delay time is the time duration from the midpoint of the d (disable) input signal to 10% of the output tri-state resp onse. see figure 7 , page 12 . 32 parameter has been characteri zed but not production tested. 33 parameter is guaranteed by design but not production tested.
analog integrated circuit device data 12 freescale semiconductor 33887 electrical characteristics timing diagrams timing diagrams figure 6. output delay time figure 7. disable delay time figure 8. output switching time figure 9. active curre nt limiting versus temperature (typical) time 0 5. 0 0 v pwr t d(o n) 50% 90% 50 % 10% t d(o ff ) ??? 0 v 5.0 v 0 t r 0 v pwr 90% 10% 10 % 90 % t f i m a x , o u t p u t c u r r e n t ( a ) 6.6 2.5 160 175 thermal shutdown t j , junction temperature ( o c) i lim , 6.5 i lim , current (a) 4.0 operation within this region must be 150 limited to nonrepetitive events not to exceed 30 seconds
analog integrated circuit device data freescale semiconductor 13 33887 electrical characteristics timing diagrams figure 10. operating states figure 11. example short circuit detection detail on low-side mosfet active current limiting >8a 6.5 short circuit detection threshold typical current limit threshold hard short detect ion and latch-off 0 in1 or in2 in2 or in1 in1 or in2 in2 or in1 in1 in2 [1] [0] [1] [0] [1] [0] [1] [0] outputs tri-stated outputs tri-stated outputs operation (per input control condition) time sf , logic out d2 , logic in d1 , logic in in n , logic in i load , output current (a) high current load being regulated via constant-off-time pwm moderate current load on low-side mosfet overcurrent minimum threshold t a t b 8.0 time i l o a d , o u t p u t c u r r e n t ( a ) typical pwm load current limiting waveform hard output short latch-off t a = tristate output off time t b = current limit blank time 6.5 hard short detect ion short circuit detect threshold t a = output constant-off time t b = output blanking time i scl short circuit detection threshold i out , current (a) typical current limiting waveform t b 5.0 t a 8.0 hard short occurs. hard short is detected during t b i lim blanking time t on 0.0 and output is latched-off.
analog integrated circuit device data 14 freescale semiconductor 33887 electrical characteristics typical switching waveforms typical switching waveforms important for all plots, the following applies: ?ch2 = 2.0 a per division ?l load = 533 h @ 1.0 khz ?l load = 530 h @ 10.0 khz ?r load = 4.0 figure 12. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 1.0 khz, and duty cycle of 10% figure 13. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 1.0 khz, and duty cycle of 50% v+=24 v f pwm =1.0 khz duty cycle=10% output voltage (out1) i out input voltage (in1) v+=24 v f pwm = 1.0 khz duty cycle = 50% output voltage (out1) i out input voltage (in1)
analog integrated circuit device data freescale semiconductor 15 33887 electrical characteristics typical switching waveforms figure 14. output voltage and current vs. input voltage at v+ = 34 v, pmw frequency of 1.0 khz, and duty cycle of 90%, showing device in current limiting mode figure 15. output voltage and current vs. input voltage at v+ = 22 v, pmw frequency of 1.0 khz, and duty cycle of 90% v+=34 v f pwm =1.0 khz duty cycle=90% output voltage (out1) i out input voltage (in1) v+=22 v f pwm =1.0 khz duty cycle=90% output voltage (out1) i out input voltage (in1)
analog integrated circuit device data 16 freescale semiconductor 33887 electrical characteristics typical switching waveforms figure 16. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 10 khz, and duty cycle of 50% figure 17. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 10 khz, and duty cycle of 90% v+=24 v f pwm =10 khz duty cycle=50% output voltage (out1) i out input voltage (in1) v+=24 v f pwm =10 khz duty cycle=90% output voltage (out1) i out input voltage (in1)
analog integrated circuit device data freescale semiconductor 17 33887 electrical characteristics typical switching waveforms figure 18. output voltage and current vs. input voltage at v+ = 12 v, pmw frequency of 20 khz, and duty cycle of 50% for a purely resistive load figure 19. output voltage and current vs. input voltage at v+ = 12 v, pmw frequency of 20 khz, and duty cycle of 90% for a purely resistive load v+=12 v f pwm =20 khz duty cycle=50% output voltage (out1) i out input voltage (in1) v+=12 v f pwm =20 khz duty cycle=90% output voltage (out1) i out input voltage (in1)
analog integrated circuit device data 18 freescale semiconductor 33887 electrical characteristics electrical performance curves electrical per formance curves figure 20. typical high-side r ds(on) versus v+ figure 21. typical low-side r ds(on) versus v+

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analog integrated circuit device data freescale semiconductor 19 33887 electrical characteristics electrical performance curves figure 22. typical quiescent supply current versus v+

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analog integrated circuit device data 20 freescale semiconductor 33887 electrical characteristics electrical performance curves table 6. truth table the tri-state conditions and the fault status are reset using d1 or d2 . the truth table uses the following notations: l = low, h = high, x = high or low, and z = high impedance (a ll output power transistors are switched off). device state input conditions fault status flag output states en d1 d2 in1 in2 fs out1 out2 forward h l h h l h h l reverse h l h l h h l h freewheeling low h l h l l h l l freewheeling high h l h h h h h h disable 1 (d1) h h x x x l z z disable 2 ( d2 ) h x l x x l z z in1 disconnected h l h z x h h x in2 disconnected h l h x z h x h d1 disconnected h z x x x l z z d2 disconnected h x z x x l z z undervoltage (34) h x x x x l z z overtemperature (35) h x x x x l z z short circuit (35) h x x x x l z z sleep mode en l x x x x h z z en disconnected z x x x x h z z notes 34 in the case of an undervoltage condition, the outputs tri-stat e and the fault status is set logic low. upon undervoltage reco very, fault status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 35 when a short circuit or overtemperatur e condition is detected, the power outputs are tri-state latched-off independent of the input signals and the fault status flag is set logic low.
analog integrated circuit device data freescale semiconductor 21 33887 functional description introduction functional description introduction numerous protection and operational features (speed, torque, direction, dynamic braking, pwm control, and closed- loop control), in addition to the 5.0 a current capability, make the 33887 a very attractive, cost-effective solution for controlling a broad range of small dc motors. in addition, a pair of 33887 devices can be used to control bipolar stepper motors. the 33887 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding ac currents. functional pin descriptions power ground and analog ground (pgnd and agnd) power and analog ground pins should be connected together with a very low impedance connection. positive power supply (v+) v+ pins are the power supply inputs to the device. all v+ pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. v+ pins have an undervoltage threshold. if the supply voltage drops below a v+ undervoltage threshold, the output power stage switches to a tri-state condition and the fault status flag is set and the fault status pin voltage switched to a logic low. when the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault status flag is automatically reset logic high. as v+ increases in value above 28 v, the charge pump performance begins to degrade. at +40 v, the charge pump is effectively non-functional. operation at this high voltage level will result in the output fets not being enhanced when turned on. this means that t he voltage on the output will be v out = (v+) ? v gs . this increased voltage drop under load will produce a higher power dissipation. fault status ( fs ) the fs pin is the device fault stat us output. this output is an active low open drain structure requiring a pull-up resistor to 5.0 v. refer to table 6, truth table , page 20 . logic input control and disable (in1, in2, d1, and d2) these pins are input control pins used to control the outputs. these pins are 5.0 v cmos-compatible inputs with hysteresis. the in1 and in2 independently control out1 and out2, respectively. d1 and d2 are complementary inputs used to tri-state disabl e the h-bridge outputs. when either d1 or d2 is set (d1 = logic high or d2 = logic low) in the disable state, outputs out1 and out2 are both tri-state disabled; however, th e rest of the circuitry is fully operational and the supply i q (standby) current is reduced to a few milliamperes. refer to table 6, truth table , and static electrical characteristics table, page 9 . h-bridge output (out1 and out2) these pins are the outputs of th e h-bridge with integrated output mosfet body diodes. th e bridge output is controlled using the in1, in2, d1, and d2 inputs. the low-side mosfets have active current limiting above the i lim threshold. the outputs also hav e thermal shutdown (tri-state latch-off) with hysteresis as well as short circuit latch-off protection. a disable timer (time t b ) used to detect currents that are higher than current limit is acti vated at each output activation to facilitate hard short detection (see figure 11 , page 13 ). charge pump capacitor (ccp) a filter capacitor (up to 33 nf) can be connected from the charge pump output pin and pgnd. the device can operate without the external capacitor, although the c cp capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and pwm frequency. enable (en) the en pin is used to place the device in a sleep mode so as to consume very low currents. when the en pin voltage is a logic low state, the device is in the sleep mode. the device is enabled and fully operational when the en pin voltage is logic high. an internal pull-down resistor maintains the device in sleep mode in the event en is driven through a high impedance i/o or an unpowered microcontroller, or the en input becomes disconnected. feedback for h-bridge (fb) the 33887 has a feedback output (fb) for ?real time? monitoring of h-bridge high-side current to facilitate closed- loop operation for motor speed and torque control. the fb pin provides current sensing feedback of the h-bridge high-side drivers. when running in forward or reverse direction, a ground referenced 1/375th (0.00266) of load current is output to this pin. through an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can ?read? the current proportional
analog integrated circuit device data 22 freescale semiconductor 33887 functional description functional pin descriptions voltage with its analog-to-digital converter (adc). this is intended to provide the user with motor current feedback for motor torque control. the resistance range for the linear operation of the fb pin is 100 < r fb < 200 . if pwm-ing is implemented using the disable pin inputs (either d1 or d2 ), a small filter capacitor (1.0 f or less) may be required in parallel with the external resistor to ground for fast spike suppression.
analog integrated circuit device data freescale semiconductor 23 33887 functional device operation operational modes functional device operation operational modes the 33887 simplified internal block diagram shown in figure 2 , page 2 , is a fully protected monolithic h-bridge with enable, fault status reporting, and high-side current sense feedback to accommodate closed-loop pwm control. for a dc motor to run, the input conditions need be as follows: enable input logic high, d1 input logic low, d2 input logic high, fs flag cleared (logic high), one in logic low and the other in logic high (to define output polarity). the 33887 can execute dynamic braking by simultaneously turning on either both high-side mosfets or both low-side mosfets in the output h-bridge; e.g., in1 and in2 logic high or in1 and in2 logic low. the 33887 outputs are capable of providing a continuous dc load current of 5.0 a from a 28 v v+ source. an internal charge pump supports pwm frequencies to 10 khz. an external pull-up resistor is required at the fs pin for fault status reporting. the 33887 has an analog feedback (current mirror) output pin (the fb pin) that provides a constant- current source ratioed to the active high-side mosfet. this can be used to provide ?real time? monitoring of load current to facilitate closed-loop operation for motor speed/torque control. two independent inputs (in1 and in2) provide control of the two totem-pole half-bridge outputs. two disable inputs (d1 and d2 ) provide the means to force the h-bridge outputs to a high-impedance state (all h-bridge switches off). an en pin controls an enable function that allows the 33887 to be placed in a power-conserving sleep mode. the 33887 has undervoltage shutdown with automatic recovery, active current limiti ng, output short-circuit latch- off, and overtemperature latch-off. an undervoltage shutdown, output short-circuit latch-off, or overtemperature latch-off fault condition will cause the outputs to turn off (i.e., become high impedance or tri-stated) and the fault output flag to be set low. either of the disable inputs or v+ must be ?toggled? to clear the fault flag. active current limiting is a ccomplished by a constant off- time pwm method employing active current limiting threshold triggering. the active current limiting scheme is unique in that it incorporates a junction temp erature-dependent current limit threshold. this means the active current limiting threshold is ?ramped down? as the junction temperature increases above 160 c, until at 175 c the current will have been decreased to about 4.0 a. above 175 c, the overtemperature shutdown (latch-off) occurs. this combi nation of features allows the device to remain in operation for 30 seconds at junction temperatures above 150 c for nonrepetitive unexpected loads.
analog integrated circuit device data 24 freescale semiconductor 33887 functional device operation protection and di agnostic features protection and diagnostic features short circuit protection if an output short circuit condition is detected, the power outputs tri-state (latch-off) independent of the input (in1 and in2) states, and the fault status output flag is set logic low. if the d1 input changes fr om logic high to logic low, or if the d2 input changes from logic low to logic high, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic high state. the output stage will always switch into the mode defined by the input pins (in1, in2, d1, and d2 ), provided the device junction temperature is wit hin the specified operating temperature range. active current limiting the maximum current flow under normal operating conditions is internally limited to i lim (5.2 a to 7.8 a). when the maximum current value is re ached, the output stages are tri-stated for a fixed time (t a ) of 20 s typical. depending on the time constant associated wit h the load characteristics, the current decreases during the tr i-state duration until the next output on cycle occurs (see figures 11 and 14 , page 13 and page 15 , respectively). the current limiting threshold value is dependent upon the device junction temperature. when -40 c t j 160 c, i lim is between 5.2 a to 7.8 a. when t j exceeds 160 c, the i lim current decreases linearly down to 4.0 a typical at 175 c. above 175 c the device overtemperature circuit detects t lim and overtemperature shutdown occurs (see figure 9 , page 12 ). this feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160 c. output avalanche protection an inductive fly-back event, namely when the outputs are suddenly disabled and v+ is lost, could result in electrical overstress of the drivers. to prevent this the v+ input to the 33887 should not exceed the maximum rating during a fly- back condition. this may be done with either a zener clamp and/or an appropriately valued input capacitor with sufficiently low esr. overtemperature shutdown and hysteresis if an overtemperature condit ion occurs, the power outputs are tri-stated (latched-off) and the fault status flag is set to logic low. to reset from this condition , d1 must change from logic high to logic low, or d2 must change from logic low to logic high. when reset, the outp ut stage switches on again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. note resetting from the fault condition will clear the fault status flag.
analog integrated circuit device data freescale semiconductor 25 33887 typical applications typical applications figure 23 shows a typical application schematic. for precision high-cu rrent applications in harsh, noisy environments, the v+ by-pass capacitor may need to be substantially larger. figure 23. 33887 typical application schematic + + dc motor agnd out1 fb pgnd v+ ccp out2 en d2 d1 fs in1 in2 33887 v+ 33 nf 1.0 f 100 fb in2 in1 fs d1 en d2 47 f
analog integrated circuit device data 26 freescale semiconductor 33887 packaging soldering information packaging soldering information the 33887 packages are designed for thermal performance. the significant feat ure of these pa ckages is the exposed pad on which the power die is soldered. when soldered to a pcb, this pad prov ides a path for heat flow to the ambient environment. the more copper area and thickness on the pcb, the bett er the power dissipation and transient behavior will be. example characterization on a double-sided pcb: bottom side area of copper is 7.8 cm 2 ; top surface is 2.7 cm 2 (see figure ); grid array of 24 vias 0.3 mm in diameter . figure 24. pcb test layout top side bottom side
analog integrated circuit device data freescale semiconductor 27 33887 packaging packaging dimensions packaging dimensions important for the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98a drawing number below vw suffix 20-pin hsop 98ash70702a issue b
analog integrated circuit device data 28 freescale semiconductor 33887 packaging packaging dimensions vw suffix 20-pin hsop 98ash70702a issue b
analog integrated circuit device data freescale semiconductor 29 33887 packaging packaging dimensions fk (pb-free) suffix 36-pin pqfn 98asa10583d issue c
analog integrated circuit device data 30 freescale semiconductor 33887 packaging packaging dimensions fk (pb-free) suffix 36-pin pqfn 98asa10583d issue c
analog integrated circuit device data freescale semiconductor 31 33887 packaging packaging dimensions ek suffix (pb-free) 54-pin soicw exposed pad 98asa10506d issue c
analog integrated circuit device data 32 freescale semiconductor 33887 packaging packaging dimensions ek suffix (pb-free) 54-pin soicw exposed pad 98asa10506d issue c
analog integrated circuit device data freescale semiconductor 33 33887 additional documentation thermal addendum (rev 2.0) additional documentation thermal addendum (rev 2.0) introduction this thermal addendum is provided as a supplement to the mc33887 technical data sheet. the addendum provides ther mal performance information that may be critical in the design and developm ent of system applicat ions. all electrical, application, and packaging information is provided in the data sheet. packaging and thermal considerations the mc33887 is offered in a 20 pin hsop exposed pad, single die package. there is a single heat source (p), a single junction temperature (t j ), and thermal resistance (r ja ). the stated values are solely for a thermal performance comparison of one package to another in a standardized en vironment. this methodology is not meant to and will not predict the perfor mance of a package in an application- specific environment. stated values were obtained by measurement and simulation according to the standards listed below. standards notes: 1.per jedec jesd51-2 at natural convection, still air condition. 2.2s2p thermal test board per jedec jesd51-5 and jesd51-7. 3.per jedec jesd51-8, with the board temperature on the center trace near the center lead. 4.single layer thermal test board per jedec jesd51-3 and jesd51-5. 5.thermal resistance between the die junction and the exposed pad surface; cold plate attached to the package bottom side, remaining surfaces insulated figure 25. thermal land pattern for direct thermal attachment according to jesd51-5 20-pin hsop-ep 33887hsop note for package dimensions, refer to the 33887 device data sheet. vw suffix 98ash70273a 20-pin hsop-ep t j = r ja . p table 7. thermal performance comparison thermal resistance [ c/w] r ja (1) , (2) 20 r jb (2) , (3) 6.0 r ja (1) , (4) 52 r jc (5) 1.0 1.0 1.0 0.2 0.2 soldermast openings thermal vias connected to top buried plane * all measurements are in millimeters 20 terminal hsop-ep 1.27 mm pitch 16.0 mm x 11.0 mm body 12.2 mm x 6.9 mm exposed pad
analog integrated circuit device data 34 freescale semiconductor 33887 additional documentation thermal addendum (rev 2.0) figure 26. thermal test board device on thermal test board r ja is the thermal resistance between die junction and ambient air. r js is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package (see figure 26 ). en agnd in2 d1 c cp v+ out2 out2 d2 pgnd pgnd fs v+ out1 out1 fb pgnd pgnd in1 v+ 1 2 3 4 5 6 7 8 9 10 20 19 16 15 14 13 12 11 18 17 tab tab 33887 pin connections 20-pin hsop-ep 1.27 mm pitch 16.0 mm x 11.0 mm body 12.2 mm x 6.9 mm exposed pad a material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a : cu heat spreading areas on board surface ambient conditions: natural convection, still air table 8. thermal resistance performance thermal resistance area a (mm 2 ) c/w r ja 0.0 52 300 36 600 32 r js 0.0 10 300 7.0 600 6.0
analog integrated circuit device data freescale semiconductor 35 33887 additional documentation thermal addendum (rev 2.0) figure 27. device on thermal test board r ja figure 28. transient thermal resistance r ja device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 heat spreading area a [mm2] thermal resistance [oc/w ] 0 300 600 r ja x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time[s] thermal resistance [oc/w]
analog integrated circuit device data 36 freescale semiconductor 33887 revision history revision history revision date description 10.0 7/2005 ? added thermal addendum & converted to freesc ale format, revised pqfn drawing, made several minor spelling correction. added 33887a 11.0 11/2006 ? updated ordering information block with new epp information ? changed the supply/ operating voltage from 40 v to 28 v ? updated all package drawings to the current revision ? adjusted to match device performance characteristics ? updated the document to the prev ailing freescale form and style ? removed peak package reflow temperature duri ng reflow (solder reflow) parameter from maximum ratings on page 7 . ? added note (8) ? added mcz33887ek/r2 to the ordering information on page 1 ? removed the 33887a from the data sheet and dele ted product variation section now that is no longer needed. 12.0 1/2007 ? changed the third paragraph of the introduction on page 1 ? altered feature number 1 on page 1 ? added feature number 2 on page 1 ? changed maximum supply voltage (1) to 0.3 to 40 v ? added note (1) ? changed note (16) ? added a third paragraph to positive power supply (v+) on page 21 ?replaced figure 20 , figure 21 , and figure 22 with updated information. 13.0 10/2008 ? added part number mc33887avw/r2 to ordering information table on page 1. 14.0 3/2011 ? removed part numbers mc33887apvw/r2, mc33887dh/r2, mc33887dwb/r2, mc33887avw/ r2, mc33887pnb/r2 and mcz33887ek/r2 and replaced with part numbers mc33887apvw/r2, mc33887pfk/r2 and mc33887pek/r2 in ordering information table on page 1.
mc33887 rev. 14.0 3/2011 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007 - 2011. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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